Electronic Power Supply High Suppression Ratio Voltage Reference Source Design Technology Advances

Electronic Power Supply High Suppression Ratio Voltage Reference Source Design Technology Advances

Fig. 1 Principle of voltage reference based on new self-regulation technology


Figure 2 chip photo


Figure 3 Power Supply Rejection Test Results for Voltage References

The 2014 IEEE-CICC (Custom Integrated Circuits Conference) conference was recently held in San Jose, California, USA. The CICC conference is one of the most important conferences in the field of IC design. It has been held annually since 1988. The conference covers IC design, simulation, manufacturing, MEMS, and bioelectronics. The Institute of Programmable Chips and Systems, Institute of Electronics, Chinese Academy of Sciences, made breakthroughs in the design of high power supply rejection ratio voltage references. At the conference, A-115dB PSRR CMOS Bandgap Reference With a Novel Voltage Self-Regulating Technique was reported.

The reference voltage source is a very important module in high-speed digital-analog hybrid chips. The stability of the reference voltage directly affects the performance of the entire system. Faced with the complex noise environment in a digital-analog hybrid system, the reference source must have a high power supply rejection ratio to provide a stable voltage reference for high-speed digital-analog hybrid chips. In the traditional high power supply rejection ratio reference design, an LDO (Low Dropout Linear Regulator) is used as a reference source to provide a locally stable power supply to increase the power supply rejection ratio of the reference source.

Although this method is simple and practical, it requires the use of an additional operational amplifier, which has high power consumption and large area. However, with the rise of wearable devices and mobile devices, SoC systems have become more complex. More high-speed digital circuits, RF circuits, and switched capacitor circuits are integrated on the same silicon chip. Analog circuits need to face more. High-frequency noise interference, but also more demanding power consumption and area. This brings a new challenge to the design of the reference source circuit - how to achieve a high power supply rejection ratio over a large bandwidth with low power consumption and small area.

In view of the above difficulties, this paper proposes a new self-regulation technique that achieves a reference source with a high power supply rejection ratio without the use of filter capacitors, LDOs, and op amps. The use of a new self-regulator circuit to provide a local power supply for the reference source effectively improves the low/high-frequency power supply rejection ratio of the reference source under low power consumption and small area.

The voltage reference diagram based on the new self-regulation technology is shown in Figure 1. The self-regulating technology first converts the voltage fluctuation of the power supply into a current, and then bypasses to the ground through the low-resistance branch (shown by the shaded part in FIG. 1 ), thereby obtaining a clean local power supply. The technology eliminates the traditional method of using LDOs, greatly saving power consumption and area, and has a significant effect in suppressing power supply noise. This self-regulating technology can also be used to increase the power supply rejection ratio of other power supply noise-sensitive circuits (such as comparators, operational amplifiers, etc.).

The overall circuit is designed using a 0.18μm standard CMOS process. The photo of the chip is shown in Figure 2. Reference source power supply rejection ratio test results are shown in Figure 3. The power supply rejection ratio is -115dB at low frequencies and -90dB at 10MHz. The test results are superior to other similar types of literature.

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